For instance, as illustrated in FIG. 16, a pixel array 102 of an active matrix image display device 101 is provided with a plurality of data signal lines SL1–SLn, a plurality of scanning signal lines GL1–GLm, and pixels PIX (1, 1) through PIX (n, m) which are provided in a matrix manner and corresponding to respective pairs of the data signal lines SL1–SLn and the scanning signal lines GL1–GLm.
A control circuit 106 outputs an image signal DAT which indicates an image. Here, in a time division manner, the image signal DAT transmits the sets of image data D each indicating the display condition of the corresponding pixel displaying an image, and the control circuit 106 outputs a clock signal SCK and a start pulse signal SSP, as timing signals for correctly displaying the image signal DAT by the pixel array 102, to a data signal line drive circuit 103, and also outputs a clock signal GCK and a start pulse signal GSP to a scanning signal line drive circuit 104.
Also, the scanning signal line drive circuit 104 sequentially selects the scanning signal lines GL1–GLm of the pixel array 102, in sync with timing signals such as the clock signal GCK.
Moreover, the data signal line drive circuit 103 is operated in sync with timing signals such as the clock signal SCK, so as to specify the timings in accordance with the respective data signal lines SL1–SLn, and sample the image signals DAT at these timings. Further, the data signal line drive circuit 103 amplify the results of the sampling as occasion demands, and then writes the results into the data signal lines SL1–SLn.
In contrast, a pixel PIX(i, j) controls its brightness in accordance with the data written in the corresponding data signal line SLi, during a period (horizontal period) when the corresponding scanning signal line GLj is selected. This enables to display the image specified by an image signal DAT on the pixel array 102. Here, i is an arbitrary integral number not more than the number of the data signal lines SL1–SLn, and j is an arbitrary integral number not more than the number of the scanning signal lines GL1–GLm.
As illustrated in FIG. 17, provided that a start pulse signal SSP is supplied to a first stage L1 of a shift register SR of the data signal line drive circuit 103, the shift register SR shifts the outputs of stages L1 through L(n−1) to the next stages Ln+1 through Ln, respectively, with a predetermined shift cycle indicated as a clock signal SCK. As a result, as illustrated in FIG. 18, the output signal waveforms of latch circuits L1–Ln constituting the respective stages of the shift register SR become respective signal waveforms O1–On in which the phase difference between neighboring waveforms is equal to one shift cycle.
The output signals O1–On are, as FIG. 17 shows, subjected to the adjustment of pulse width in respective wave shaping circuits WE1–WEn, and then the output signals O1–On are subjected to buffering in respective buffer circuits BF1–BFn, so as to be outputted as timing signals T1–Tn.
In contrast, the data signal line drive circuit 103 is provided with a sampling section 111 composed of sampling units SU1–SUn corresponding to the respective data signal lines SL1–SLn. A sampling unit SUi outputs an image signal DAT to a data signal line SLi, during a period indicated by a timing signal Ti. For this reason, the result of the sampling of the image signal DAT, at the timing when the timing signal Ti indicates the stop of outputting, is written into a pixel PIX(i, j).
Here, the control circuit 106 outputs a clock signal SCK which indicates shift cycle in sync with sampling cycle of the image signal DAT. This enables the data signal line drive circuit 103 to properly sample the image signal DAT, so that the image display device 101 can display the image specified by the image signal DAT.
By the way, when the resolution of the image signal DAT varies, the number of pixels constituting one image varies in longitudinal and lateral directions. Thus, the number of scanning periods for displaying one image by the image signal DAT and the number of sampling timings in one scanning period also vary.
Moreover, to display images of different image signals DAT in an identical size, it is necessary to change the distance between neighboring pixels (distance between the centers of the respective pixels). However, being different from CRTs (Cathode-Ray Tubes), in the image display device 101, the distance between the pixels PIX is fixed at the distance between the data signal lines SL1–SLn or the scanning signal lines GL1–GLm, so that it is not possible to change actual signal line resolution.
Thus, to drive the pixel array 102 with actual signal line resolution of the image display device 101 on the occasion of the input of an image signal DAT having signal line resolution lower than the actual signal line resolution, there is an image display device which has been proposed (cf. Japanese Laid-Open Patent Application No. 6-274122/1994 (Tokukaihei 6-274122); published on Sep. 30, 1994), arranged in such a manner that a control circuit is provided between a signal source of an image signal DAT and a data signal line drive circuit, so that, when an image signal DAT having signal line resolution lower than the actual signal line resolution of the image display device 101 is inputted, in order to interpolate necessary image data, the control circuit generates an interpolating image signal and an interpolating clock in sync with the same, and supplies them to the data signal line drive circuit.
However, in this conventional art, the interpolating image signal and the interpolating clock are generated in order to interpolate necessary image data, even in low-resolution mode. Thus, in this case, the number of pulses of a clock signal (clock signal after the interpolation) in one horizontal period, the clock signal being supplied to the data signal line drive circuit, is identical with the number on the occasion of high-resolution mode. For this reason, it is difficult to sufficiently reduce the operating speed of a circuit (such as the foregoing control circuit) for supplying the image signal DAT to the data signal line drive circuit, and it is also difficult to reduce the power consumption.
Furthermore, in this case, the data signal line drive circuit generates the timing signals Ti in accordance with the output signals from all stages (latch circuits L1, L2, . . . ) of the shift register SR in FIG. 16, both in high-resolution mode and low-resolution mode. This again causes the difficulty in reducing the power consumption of the data signal line drive circuit.